With the trend of scaling down devices for higher density, many integrated circuits have both low and high voltage requirements. The low voltage is required for normal operation of the circuit. Other operations of the circuit require the higher voltage. This higher voltage may, for example, be used to write, restore, or refresh a high voltage stored in a memory cell. The power supply providing the high voltage may be a pumped voltage supply, or may be provided externally. An example of such an integrated circuit is a complementary metal oxide semiconductor ("CMOS") dynamic random access memory ("DRAM"). Typical low and high voltages are 3V and 5V, respectively.
FIG. 1 is a schematic diagram of a circuit that converts a low voltage signal varying between 0V and VCC (e.g. 3V) to a high voltage signal varying between 0V and VCCP (e.g. 5V). Briefly, gate electrodes of transistors 10, 12 and 14 are coupled to receive an input signal IN. VCC is coupled to ground (typically 0V) through a series source-drain path of complementary transistors 12 and 14. A node 13 is located at the drain electrodes of transistors 12 and 14. Node 13 is coupled to a gate electrode of a transistor 16.
A node 18 is coupled to ground through source-drain paths of series transistors 16 and 20. A gate electrode of transistor 20 is coupled to receive VCC. Node 18 is coupled to a gate electrode of a P-channel transistor 22. VCCP is coupled to node 18 through a source-drain path of a P-channel transistor 24. A gate electrode of transistor 24 is coupled to a node 26. The bodies (or N-wells) of transistors 22 and 24 are connected to VCCP.
Node 26 is coupled to VCCP through a source-drain path of transistor 22. Node 26 is coupled to ground through source-drain paths of series transistors 28 and 10. A node 30 is coupled to the drain electrode of transistor 10. A gate electrode of transistor 28 is coupled to receive VCC. A node 32 is coupled to the drain electrode of transistor 16 and the source electrode of transistor 20. An output signal OUT is provided at node 18.
Transistors 12 and 14 form an inverter. When the signal IN is supplied to transistors 12 and 14, the voltage at node 13 is the opposite state of the signal IN. For example, if a voltage of signal IN is VCC, then the voltage at node 13 is 0V.
Referring to the operation of the FIG. 1 circuit, when signal IN is VCC, transistor 10 is turned on to pull node 30 to 0V. Since transistor 28 is configured to be on (its gate-source voltage is greater than a threshold voltage Vt.sub.N drop), node 26 will be pulled to 0V through the source-drain path of transistor 10.
Transistors 12 and 14 invert the high signal IN to provide 0V at node 13. Since this is coupled to the gate electrode of transistor 16, it turns off. Thus node 18 is not pulled to 0V through the source-drain path of transistor 20. However, node 26 provides 0V to the gate electrode of transistor 24 to turn it on (the gate-source voltage is more negative than a threshold voltage Vt.sub.p). The source-drain path of transistor 24 pulls node 18 to VCCP.
Meanwhile, node 18 supplies VCCP to the gate electrode of transistor 22. The gate-source voltage is not less than a threshold voltage Vt.sub.p, so transistor 22 is turned off. Node 26 is pulled closer to 0V. The output signal OUT provided at node 18 is VCCP.
When the voltage of signal IN is 0V, it turns off transistor 10 and unclamps nodes 26 and 30 from 0V. The 0V of the signal IN is inverted by transistors 12 and 14 to provide VCC to the gate of transistor 16. Transistor 16 is turned on to pull nodes 18 (through turned-on transistor 20) and 32 to 0V.
Node 18 provides 0V to the gate electrode of transistor 22 to turn it on (the gate-source voltage is more negative than a threshold voltage Vt.sub.p). As a result, node 26 is clamped to VCCP, which is coupled to the gate electrode of transistor 24. Transistor 24 is thereby turned off since the gate-source voltage is more negative than a threshold voltage Vt.sub.p. Thus, node 18 is pulled closer to 0V. Output signal OUT provided by node 18 is 0V.
The circuit shown in FIG. 1 suffers from slow speed since nodes 30 and 32 cannot be quickly pulled to VCC because they are not directly coupled to VCC. Pulling nodes 30 and 32 to VCC would speed up the transition of respective nodes 26 and 18 to VCCP.
Therefore, it is a general object of the present invention to overcome the above problems.
The further object of the present invention is to minimize current flow from a power supply providing VCCP to another potential, such as ground.